The present invention relates to a semiconductor memory device, and more particularly, to a multi-bit data block testing circuit and method for selecting a bit pattern of test data from adjacent cell blocks by receiving the test data from a test data input port.
In prior art semiconductor memory devices, input/output operations are typically performed using multi-bit data blocks, that is, data which is accessed in four-bit, eight-bit, sixteen-bit, thirty two-bit and similar blocks. Also, prior art methods of simultaneously testing these multi-bit data blocks have been used to reduce the time and cost of testing multi-bit semiconductor memory devices.
A prior art multi-bit data block testing circuit and a prior art determining circuit used therein are shown in FIGS. 1 and 2, respectively, and are described further hereinbelow in the Detailed Description. Briefly, cell blocks in the semiconductor memory device under test are tested by the prior art testing circuit using integrated input/output bits. This approach leads to several problems. First, since only identical test data patterns are written into and read from the cell blocks, a failure caused by a faulty connection between bits cannot be detected. Second, the prior art determining circuit cannot detect simultaneous failures between one of two comparing pairs of data signals. For example, suppose that a failure exists in each of a first and a third cell block. When the multi-bit test data is written as "high" data values, the data signals output therefrom are asserted "low." However, the output signal from the determining circuit 30 will also be asserted "low" and the failures will go undetected.